Analog-to-digital converters (ADCs) convert time-discrete analog input values to a digital form. A type of ADC, the successive approximation register (SAR) ADC, digitizes the analog input values using a successive approximation search algorithm. While the internal circuitry of the SAR ADC may run at a higher frequency (such as several megahertz (MHz), for example), the sample rate of the SAR ADC is generally a fraction of that frequency (such as several kilohertz (kHz), for example) due to the successive approximation search algorithm used. For example, normally each bit of the SAR ADC is fully realized prior to proceeding on to the next bit.
In general, each bit-weight of a successive approximation register (SAR) arrangement of a SAR ADC may be represented by a physical element (e.g., capacitor, resistor, current source, etc.). A search algorithm may be used with the physical elements to determine the closest digital approximation to an analog input value. While this technique may be simple to implement, it is not always the most power efficient or the fastest. Split-capacitor techniques can be more power efficient, but have a higher complexity. Further, control logic and/or error correction can be complex, linearity can suffer, and excessive chip area can be used for some implementations.